This invention relates to a dynamic type semiconductor memory device.
Many computers utlize dynamic RAM as main memory. The memory cell of the dynamic RAM comprises a capacitor for storing charges of an amount corresponding to a logic value and a transfer gate for the movement of charges to and from the capacitor. Generally, the memory cell of the dynamic RAM comprises few circuit elements so that it does not occupy much area. With dynamic RAM, more memory cells than in the case of a static RAM, for instance, can be provided in a single package, and the cost required for storing one bit data is inexpensive.
The dynamic RAM has many memory cells and a control circuit for selectively operating the memory cells at the time of the reading and writing operations. Heretofore, these memory cells and control circuit have been implemented with n-channel MOS transistors and MOS capacitors which can be readily fabricated.
Where minute n-channel MOS transistors and MOS capacitors are formed to increase the memory capacity of the dynamic RAM, there arises the following problem.
When a high level voltage is applied between the source and drain of a minute n-channel MOS transistor, excited carriers (i.e., hot electrons) are liable to intrude into and be trapped by an oxide insulator on the channel. Many n-channel MOS transistors in the dynamic RAM operate in the operating range of a pentode characteristic, in which the drain current is saturated, so that the dynamic RAM is subject to erroneous operation due to the trapping. Particularly, the trapping that occurs in an n-channel MOS transistor used as the transfer gate of a memory cell, permits erroneous data to be written in and read out from the capacitor of the memory cell.
In another aspect, a voltage signal which is applied to the gate of a MOS transistor in the memory cell via a word line does not rise quickly and also the electric conductivity of the channel of the transistor is low, so that high speed read/write operation cannot be obtained.
Further, the capacitor does not have an electrode area large enough to store charges sufficient for the discrimination of a logic value.
In the prior art dynamic RAM which is fabricated by taking the above problems into considerations, the memory cells and control circuit are partly constituted by p-channel MOS transistors, in which carriers are not so easily excited as in n-channel MOS transistors. The MOS capacitor in the memory cell has one end connected to a bit line through the current path of a p-channel MOS transistor which is used as a transfer gate, while its other end is grounded. The gate of the p-channel MOS transistor is connected to a word line. During a stand-by period of the memory cell, a precharging voltage is applied to the bit line. This voltage is equal to the voltage applied to the word line to render the p-channel MOS transistor nonconductive. When operating the memory cell, a low level voltage is applied to the word line to render the p-channel MOS transistor conductive. With this arrangement, the p-channel MOS transistor operates in the range of a triode characteristic, in which the drain current is not saturated, so that the operation speed can be improved.
With the dynamic RAM mentioned, however, it has been impossible to apply a charging voltage to the capacitor efficiently when writing data. More specifically, the capacitor in the memory cell is connected to the bit line through the current path of the p-channel MOS transistor. A voltage drop corresponding to the threshod voltage of the transistor occurs, so that only a voltage equal to the potential on the bit line minus the threshold voltage of the transistor can be applied to the capacitor. Denoting the potential level on the bit line by VC and the threshold voltage of the p-channel MOS transistor by VTH, a voltage (VC-VTH) is supplied to the capacitor. Voltage of the level VC may be applied to the capacitor by merely providing means for bootstrapping the potential on the word line to the level (VC+VTH). However, in view of the voltage drop across the transfer gate transistor corresponding to the threshold voltage VTH, a node with potential thereon bootstrapped to a level in excess of (VC+2VTH) is necessary. This means a disadvantage in that a high voltage must be applied to the minute MOS transistor.